The advancement of future detector arrays in new materials is hindered by the readout requirement of the many signals emanating from the array. For small array sizes, wire bonding or wire interconnects to array periphery can be used to read out individual detectors; but for larger arrays, a multiplexer circuit is needed.
For silicon detectors, CCD multiplexers have been used for readout. However, the silicon detector is generally limited to the visible and near IR portion of the spectrum. CCD multiplexers are often limited by either signal capacity or operating temperature. Additionally, the monolithic integration of the detector and multiplexer places constraints on detector fill-factor or readout smear.
The switched-FET type of multiplexer (typically silicon CMOS) has been used to read out HgCdTe detector arrays operating in the IR wavelength region. In that case, the detectors and multiplexers are fabricated in separate processes and then interconnected through the use of a solder (or indium) "bump" bond. Bump bonding is a fairly well-established technology for array sizes up to 256.times.256 pixels. For larger arrays, bonding yields become a concern. In addition, the physical size of the bump can place a limitation on pixel spacing. A more serious concern is the matching of thermal expansion coefficients between the detector array material and the multiplexer material. In this case, failure of the hybridized imager can occur after repeated thermal cycling.
An emerging potential technology for integration of detector arrays and multiplexers is the epitaxial growth of the detector material on the readout multiplexer (or vice-versa). For example, HgCdTe on sapphire has been tried with modest success. However, there are three difficulties with this approach. First, the lattice constant of the detector material must match that of the readout material. This seriously limits the choice of multiplexer and detector material combination, though it can be relieved somewhat through the use of strained layer interfaces. Second, from a manufacturing perspective, the process yield of the multiplexer fabrication M is multiplied by the yield of the detector material growth D, which in turn is multiplied by the detector fabrication F yield. Thus, the overall manufacturing yield MDF can be expected to be poor due to the sequential processing. Third, the thermal expansion mismatch in the otherwise lattice matched materials can be expected to again lead to thermal cycling reliability problems.
More recent developments relate to a lift-off process for removing a very thin film of semiconductor material so that it may be transferred to a semiconductor substrate of different composition. See U.S. Pat. Nos. 4,846,931 and 4,883,561 to Thomas J. Gmitter and Eli Yablonovitch. The first patent discloses a method for removing an epitaxial film from a single crystal substrate upon which it is grown using a thin release layer (.ltoreq.1000 .ANG.) and applying a polymeric support layer on the epitaxial film after it is grown. The polymeric support layer is under tension over the epitaxial film to be lifted off so that, as the thin release layer is etched away progressively from the edges, the polymeric support layer will curve away from the single crystal substrate, thus lifting the epitaxial thin film.
That film thus lifted may be a single layer or multiple epitaxial layers and may be metallized for making electrical contacts to an integrated circuit formed in the thin film. That integrated circuit thus formed and lifted off a single crystal substrate may then be attached by an adhesive or other force to a structure of different material, such as an optical fiber. The second patent cited above, which is a continuation-in-part of the first, teaches adhering the thin film on a second substrate, typically different in composition than that of the thin film.
While the impetus for the present invention has been the fabrication of large photodetector arrays with an integrated circuit for accessing the array, the solution to the problem has more general application to any need of separately fabricating two planar semiconductor circuits, laminating the planar semiconductor circuits with a layer of planarizing adhesive, and then providing electrical connections between the circuits for interaction. The ability to optimize the performance of each circuit and/or the fabrication process for each is but one advantage. A more general advantage is the ability to provide a more compact structure for the interactive circuits.